This application claims priority under 35 USC § 119 to Korean Patent Application No. 2006-54272, filed on Jun. 16, 2006 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and more particularly, to controlling execution of an additional function concurrently during execution of a refresh operation in a semiconductor memory device such as a dynamic random access memory device (DRAM).
2. Background of the Invention
Semiconductor memory devices, and especially DRAMs (dynamic random access memories), refresh each memory cell at regular intervals in order to retain data. A refresh operation of a semiconductor memory device may be categorized into an auto-refresh operation and a self-refresh operation.
A semiconductor memory device performs an auto-refresh operation when an external controller applies a refresh signal to the semiconductor memory device in a steady mode. In that case, a row of memory cells of a memory cell array are refreshed for each auto-refresh operation. A counter of the semiconductor memory device increases a row address for consecutive auto-refresh operations. Thus, when the counter of the semiconductor memory device reaches the end row of the memory cell array, the counter returns to a first row of the memory cell array.
In comparison, when the semiconductor memory device does not operate for longer than a predetermined period of time, an internal refresh signal is periodically generated so that the semiconductor memory device performs a self-refresh operation.
FIG. 1 is a block diagram of a conventional semiconductor memory device. Referring to FIG. 1, when the semiconductor memory device performs a read/write operation, an address register 11 receives an externally generated address ADD in response to an active signal ACT and a read/write signal RD/WR, divides the address ADD into a row address RA and a column address CA, and outputs the row address RA and the column address CA to a row decoder 12 and a column decoder 13, respectively. During an auto-refresh operation, the address register 11 does not output such addresses RA and CA to the row decoder 12 or the column decoder 13 since a refresh circuit portion 20 generates an internal row address IRA to perform a refresh operation.
During an active read/write operation, the row decoder 12 receives the row address RA from the address register 11 in response to the active signal ACT, decodes the row address RA, and designates a specific row of memory cells of a memory cell array 14 for the read/write operation. During the auto-refresh operation, the row decoder 12 receives the internal row address IRA from the refresh circuit portion 20 in response to an auto-refresh signal ARF and designates a row of memory cells of the memory cell array 14 to be refreshed.
The column decoder 13 receives the column address CA from the address register 11, decodes the column address CA, and designates a specific column of memory cells of the memory cell array 14 for the read/write operation. However, since the memory cells are refreshed a row at a time, the column decoder 13 does not operate during the refresh operation.
The memory cell array 14 includes a plurality of word lines, which are arranged in rows, and a plurality of bit lines, which are arranged in columns. Memory cells are arranged at respective intersections between the word lines and the bit lines. The memory cell array 14 further includes a plurality of sense amplifiers that sense and amplify data from the memory cells.
The memory cells of a word line of the memory cell array 14 are selected by the row decoder 12, and the sense amplifier is selected by the column decoder 13. The sense amplifier selected by the column decoder 13 amplifies data DQ of the selected memory cell and outputs the amplified data DQ to an external device in response to a read signal RD. Alternatively, the sense amplifier stores data DQ input from the external device into the selected memory cell in response to the write signal WR. The RD/WR signal is generated from a command decoder 17 to a data input/output portion 15.
Also, the sense amplifiers amplify data stored in the memory cells of the word line indicated by the refresh circuit portion 20 and re-store the amplified data therein when the semiconductor memory device performs the refresh operation.
A mode register 16 receives a mode register set (MRS) signal MRS from the command decoder 17 upon power-up of the semiconductor memory device. The mode register 16 decodes mode register set codes which are applied at address lines by an external device in response to the mode register set signal MRS and stores fundamental operational modes of the semiconductor memory device. The mode register set codes may be applied at address lines ADD of the address register 11 or may be applied as data DQ at the data input/output portion 15.
The command decoder 17 analyzes a command COM from the external device to generate the mode register set signal MRS that is an initial set signal of the semiconductor memory device to the mode register 16. The command decoder 17 also generates the auto-refresh signal ARF to the refresh circuit portion 20 and the address register 11. Further, the command decoder 17 generates the read/write signal RD/WR for controlling the data input/output portion 15.
The refresh circuit portion 20 receives the auto-refresh signal ARF from the command decoder 17 and generates the internal row address IRA to the row decoder 12. Such an internal row address IRA indicates the row of memory cells of the memory cell array 14 to be refreshed.
FIG. 2 is a detailed block diagram of the refresh circuit portion 20 of FIG. 1. The refresh operation of the conventional semiconductor memory device will now be described with reference to FIG. 2. Referring to FIG. 2, a control signal generator 21 receives the auto-refresh signal ARF from the command decoder 17 and generates a refresh selection signal PRESH and an active command PRB.
During a self-refresh operation, a self-refresh signal generator 30 receives the refresh selection signal PRESH, and periodically generates a self-refresh signal SRFHP to an internal address generator 40 for performing a self-refresh operation. The internal address generator 40 generates a refresh address CNTi corresponding to the word line WL of the memory cell array 14 to be refreshed. A refresh generator 41 receives the refresh selection signal PRESH and the self-refresh signal SRFHP and generates a refresh signal PRFH during the self-refresh operation.
On the other hand, the refresh generator 41 receives the refresh selection signal PRESH and generates the refresh signal PRFH during the auto-refresh operation. A refresh pulse generator 44 generates a refresh pulse PRCNTP in response to the refresh signal PRFH. A refresh pulse counter 45 counts the refresh pulse PRCNTP and generates the refresh address CNTi. A counter latch 46 latches the refresh address CNTi and outputs the latched refresh address CNTi in response to the refresh pulse PRCNTP.
A refresh mode generator 42 outputs a refresh mode signal SRSP in response to the refresh signal PRFH. An active generator 43 outputs an active signal PRD in response to the active command PRB and the refresh mode signal SRSP. An internal address selector 47 outputs the refresh address CNTi as the internal row address IRA to the row decoder 12 in response to the active signal PRD.
The row decoder 12 receives the internal row address IRA from the internal address generator 40 in response to the auto-refresh signal ARF and enables the corresponding word line WL of the memory cell array 14. As illustrated in FIG. 2, since the semiconductor memory device performs the refresh operation for updating data stored in the memory cells MC of the memory cell array 14, the data input/output portion 15 of FIG. 1 for reading or writing data is typically not used during the refresh operation. In other words, while the semiconductor memory device is performing the refresh operation, some blocks including the data input/output portion 15 are not used.
Also, with demand for high operating speed of the semiconductor memory device, new functions are being added to the semiconductor memory device. For example, a semiconductor memory device may additionally execute a temperature sensing function. Generally, as the operating speed of a semiconductor memory device increases, the temperature of the semiconductor memory device also increases in proportion to the operating speed.
When the temperature of the semiconductor memory device is increased, the semiconductor memory device may become inoperative. However, when the temperature sense function is added, the semiconductor memory device includes a temperature sensor to periodically check a temperature and inform an external controller of the present temperature. The external controller then generates a control command to temporarily stop or slow down the operation of the semiconductor memory device when the temperature is undesirably high. As a result, the reliability of the semiconductor memory device may be enhanced.
Another example of an additional function of a semiconductor memory device is controlling the input/output impedance of a driver circuit of the semiconductor memory device, as described in Korean Patent Publication No. 10-2005-0019453. In that case, the impedance of the driver circuit is controlled using a single external reference resistor and a single impedance code generator. However, the conventional semiconductor memory device principally employs the data input/output portion 15 shown in FIG. 1 in order to perform the additional function.
In other words, although the conventional semiconductor memory device does not use the data input/output portion 15 during the refresh operation, the impedance at the data input/output portion 15 is desired to be controlled. In the prior art, the refresh operation and the adjustment of the impedance at the data input/output portion 15 are performed during separately designated times resulting in loss of operating time.